Self-aligned vertical field-effect transistor with epitaxially grown bottom and top source drain regions

ABSTRACT

A vertical FET structure includes a bottom source-drain region disposed on a substrate of the first type; a recessed first heterostructure layer disposed on the bottom source-drain region; a first fin disposed on the bottom source-drain region; a dielectric inner spacer disposed on the recessed first heterostructure; an outer spacer disposed on the inner spacer; a high-k and metal gate layer disposed on the outer spacer, the inner spacer, and the channel layer; an interlayer dielectric oxide disposed between the first fin and the outer spacer; a recessed second heterostructure layer disposed on top of the substrate of the first type and high-k and metal gate layer; a dielectric inner spacer disposed on the recessed second heterostructure layer; and a top source-drain region layer disposed on the dielectric inner spacer and recessed second heterostructure layer resulting in the vertical FET. A method for forming the vertical FET is also provided.

FIELD OF THE INVENTION

The present invention relates to an improved vertical field-effecttransistor (FET) process. More particularly, the present inventionrelates to a self-aligned vertical FET with epitaxially grown bottom andtop source drain regions.

BACKGROUND

FETs are transistors that use an electrical field to control theelectrical behavior of the device. The fin refers in a semiconductormaterial patterned on a substrate that often has exposed surfaces thatform the narrow channel between source and drain region layers. VerticalFETs often include a vertical channel and active source and drain regionlayers arranged beneath and above the channel. A thin dielectric layerarranged over the fin separates the fin channel from the gate. Like inany transistors, there is a strong need to solve both gate lengthcontrol and junction position control problems in vertical FETs. In theconventional lateral FinFET transistors, gate length is defined bylithography or sidewall image transfer process. However, in the verticalFET architecture where the channel direction (transport direction) isarranged vertically on the substrate, none of the conventional methodsused to define gate length is applicable. The gate spacer thickness andthe source-drain extension thickness are also difficult to control inthe vertical architecture. It is critical to control them because theirthicknesses are closely related to junction positions.

SUMMARY

A method of forming a vertical field-effect transistor (FET), the methodincludes depositing a first heterostructure layer over a substrate of afirst type; depositing a channel layer over the first heterostructurelayer; depositing a second heterostructure layer over the channel layer;forming a first fin having a hard mask thereon, wherein the hard mask isdisposed on the second heterostructure layer; recessing the first andthe second heterostructure layers such that they are narrower than thefirst fin and the hard mask; filling gaps formed in the recessed firstand second heterostructure layers with a dielectric inner spacer;performing oxidation to form SiO₂ over the substrate of the first typeand the channel layer; depositing a dielectric liner; directionallyetching the dielectric liner over the SiO₂; etching the SiO₂ over thesubstrate of the first type; epitaxially growing a bottom source-drainregion layer over the substrate of the first type; conformally etchingback a hard mask liner over the bottom source-drain region layer;depositing an outer spacer on top of the bottom source-drain regionlayer; removing the SiO₂; depositing a high-k dielectric layer and metalgate layer on top of the first heterostructure layer; etching the high-kdielectric layer and metal gate layer to a level below the top hardmask; filling with interlayer dielectric (ILD) oxide and then performingCMP to the top of hard mask; etching the hard mask; and epitaxiallygrowing a top source-drain region layer over the first fin to producethe vertical FET.

A vertical field-effect transistor (FET) structure includes a bottomsource-drain region disposed on a substrate of the first type; arecessed first heterostructure layer disposed on the bottom source-drainregion; a first fin disposed on the bottom source-drain region; adielectric inner spacer disposed on the recessed first heterostructure;an outer spacer disposed on the dielectric inner spacer; a high-k andmetal gate layer disposed on the outer spacer, the dielectric innerspacer, and the channel layer; an interlayer dielectric (ILD) oxidedisposed between the first fin and the outer spacer; a recessed secondheterostructure layer disposed on top of the substrate of the first typeand high-k and metal gate layer; a dielectric inner spacer disposed onthe recessed second heterostructure layer; and a top source-drain regionlayer disposed on the dielectric inner spacer and recessed secondheterostructure layer resulting in the vertical FET.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments will be described in more detail in conjunction with theaccompanying drawings, in which:

FIG. 1 illustrates a diagram of depositing a first heterostructure layerover a substrate of a first type; depositing a channel layer over thefirst heterostructure layer; and depositing a second heterostructurelayer over the channel layer;

FIG. 2 illustrates a diagram of forming a first fin having a hard maskthereon, wherein the hard mask is disposed on the second heterostructurelayer;

FIG. 3 illustrates a diagram of recessing the first and the secondheterostructure layers such that they are narrower than the first finand the hard mask;

FIG. 4 illustrates a diagram of filling gaps formed in the recessedfirst and second heterostructure layers with a dielectric inner spacer;

FIG. 5 illustrates a diagram of performing oxidation to form SiO2 overthe substrate of the first type and the channel layer;

FIG. 6 illustrates a diagram of depositing a dielectric liner anddirectionally etching it back over the SiO2;

FIG. 7 illustrates a diagram of etching the SiO2 over the substrate ofthe first type;

FIG. 8 illustrates a diagram of epitaxially growing a bottomsource-drain region layer over the substrate of the first type;

FIG. 9 illustrates a diagram of conformally etching back a hard maskliner over the bottom source-drain region layer;

FIG. 10 illustrates a diagram of epitaxially growing additional bottomsource-drain region layer;

FIG. 11 illustrates a diagram of depositing an outer spacer on top ofthe bottom source-drain;

FIG. 12 illustrates a diagram of removing the SiO2 and depositing ahigh-k dielectric layer and metal gate layer;

FIG. 13 illustrates a diagram of etching the high-k dielectric layer andmetal gate layer to below the top hard mask;

FIG. 14 illustrates a diagram of filling with interlayer dielectric(ILD) oxide and then performing CMP to the top of hard mask; and

FIG. 15 illustrates a diagram of etching the hard mask; and epitaxiallygrowing a top source-drain region layer over the first fin to producethe vertical FET.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

It will be readily understood that components of the present invention,as generally described in the figures herein, can be arranged anddesigned in a wide variety of different configurations in addition tothe presently described preferred embodiments. Thus, the followingdetailed description of some embodiments of the present invention, asrepresented in the figures, is not intended to limit the scope of thepresent invention as claimed, but is merely representative of selectedpresently preferred embodiments of the present invention.

For the sake of brevity, conventional techniques related tosemiconductor device and IC fabrication may not be described in detailherein. Moreover, the various tasks and process steps described hereinmay be incorporated into a more comprehensive procedure or processhaving additional steps or functionality not described in detail herein.In particular, various steps in the manufacture of semiconductor devicesand semiconductor-based ICs are well known and so, in the interest ofbrevity, many conventional steps will only be mentioned briefly hereinor will be omitted entirely without providing the well-known processdetails.

In general, the various processes used to form a micro-chip that will bepackaged into an IC fall into four general categories, namely, filmdeposition, removal/etching, semiconductor doping andpatterning/lithography. Deposition is any process that grows, coats, orotherwise transfers a material onto the wafer. Available technologiesinclude physical vapor deposition (PVD), chemical vapor deposition(CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE)and more recently, and atomic layer deposition (ALD) among others.Deposition also includes a so-called epitaxial growth process whichdeposits single crystalline material on a single crystalline substrate.

Removal/etching is any process that removes material from the wafer.Examples include etch processes (either wet or dry), andchemical-mechanical planarization (CMP), and the like. A dry etchprocess such as reactive ion etching (RIE) uses chemically reactiveplasma to remove a material, such as a masked pattern of semiconductormaterial, by exposing the material to a bombardment of ions thatdislodge portions of the material from the exposed surface. The plasmais generated under low pressure (vacuum) by an electromagnetic field.

Semiconductor doping is the modification of electrical properties bydoping, for example, transistor sources and drains, generally bydiffusion and/or by ion implantation. These doping processes arefollowed by furnace annealing or rapid thermal annealing. Annealingserves to activate the implanted dopants. Selective doping of variouslayers of the semiconductor substrate allows the conductivity of thesubstrate to be changed with the application of voltage. By creatingstructures of these various components, millions of transistors can bebuilt and wired together to form the complex circuitry of a modernmicroelectronic device.

Semiconductor lithography is the formation of three-dimensional reliefimages or patterns on the semiconductor substrate for subsequenttransfer of the pattern to the substrate. In semiconductor lithography,the patterns are formed by a light sensitive polymer called aphoto-resist. To build the complex structures that make up a transistorand the many wires that connect the millions of transistors of acircuit, lithography and etch pattern transfer steps are repeatedmultiple times. Each pattern being printed on the wafer is aligned tothe previously formed patterns and slowly the conductors, insulators andselectively doped regions are built up to form the final device.

The metal gate layer is electrically insulated from the mainsemiconductor n-channel or p-channel by a thin layer insulatingmaterial, for example, silicon dioxide or high dielectric constant(high-k) dielectrics, which makes the input resistance of the transistorrelatively high.

The present invention is to be understood within the context of thedescription provided below. The description provided below is to beunderstood within the context of the Figures provided and describedabove. The Figures are intended for illustrative purposes and, as such,are not necessarily drawn to scale.

FIG. 1 illustrates a diagram of depositing a first heterostructure layer202 over a substrate of a first type 201, depositing a channel layer 203over the first heterostructure layer 202, and depositing a secondheterostructure 204 layer over the channel layer 203. The firstheterostructure layer 202 and second heterostructure layer 204 caneither be the same or different materials. The material used forheterostructure layers can be silicon germanium. The heterostructurelayer can have a thickness from about 4 to about 10 nm and ranges therebetween and the thickness of the first and second heterostructure layerscan be the same or different. The channel layer 203 can have a thicknessfrom about 10 to about 50 nm and ranges there between. The material usedfor the channel layer 203 can be a material such as silicon.

FIG. 2 illustrates a diagram of forming a first fin having a hard maskthereon 205, wherein the hard mask is disposed on the secondheterostructure layer 204. The hard mask can be silicon nitride.Alternatively, the hard mask 205 can contain multiple materials arrangedin any forms, including but not limited to silicon nitride, polysilicon,amorphous silicon, and silicon oxide. The hard mask 205 can have alateral width from about 5 to about 25 nm and ranges there between. Thefirst fin can be formed by using a reactive ion etching (RIE) process.The hard mask 205 can etched selectively using hot phosphoric acid(H3PO4).

FIG. 3 illustrates a diagram of recessing the first 202 and the second204 heterostructure layers such that they are narrower than the firstfin and the hard mask 205. FIG. 4 illustrates a diagram of filling gapsformed in the recessed first 202 and second 204 heterostructure layerswith a dielectric inner spacer 206. This can be done by firstconformally depositing inner spacer material to pinch off the gap andthen conformally etching back that material on the unwanted surfaces.The etching time can be controlled such that the material filled in thegap remains. The dielectric inner spacer 206 can be a material such assilicon-boron-carbon-nitride (SiBCN) or silicon nitride or SiCO orSiOCN. The shape of the dielectric inner spacer 206 may not be perfectlyrectangular as shown in the figures. The interface between dielectricinner spacer 206 and the recessed first heterostructure layer 202 andrecessed second heterostructure layer 204 may have a convex shapetowards the recessed heterostructure layers due to the nature of recessetching.

FIG. 5 illustrates a diagram of performing oxidation to form SiO2 207over the substrate of the first type 201 and the channel layer 203. Thechannel and bottom oxidation can use the regular dry oxidation processor a low temperature plasma oxidation process. FIG. 6 illustrates adiagram of depositing a dielectric liner and directionally etching itback 208 over the SiO2 207. FIG. 7 illustrates a diagram of etching SiO2207 over the substrate of the first type 201. FIG. 8 illustrates adiagram of epitaxially growing a bottom source-drain region layer 209over the substrate of the first type 201. The bottom source-drain regionlayer 209 can be a material such as silicon or silicon germanium. Thebottom-source drain region layer 209 is positioned directly beneathdielectric inner spacer 206. This structure helps bottom junctionformation with precisely-defined junction position.

FIG. 9 illustrates a diagram of conformally etching back the hard maskliner 208 over the bottom source-drain region layer 209. The hard maskliner 208 can be disposed on the sides of the dielectric inner spacer206. The hard mask liner 208 can be silicon nitride. The key processthat can enable precise defining of bottom junction is the oxidationprocess. The formed SiO2 207 over the substrate reserves space for thebottom source-drain region layer 209 such that the formed bottomsource-drain region layer 209 is positioned directly beneath thedielectric inner spacer 206.

FIG. 10 illustrates a diagram of epitaxially growing additional bottomsource-drain region layer 209. The highly doped bottom source-drainregion layer 209 can have a thickness of about 10 to about 50 nm andranges there between. Dopant drive-in annealing process may be performedafter bottom source-drain region layer 209 growth to form the bottomjunction.

FIG. 11 illustrates a diagram of depositing an outer spacer 210 on topof the bottom source-drain region layer 209. The bottom outer spacer 210is formed by anisotropic HDP deposition followed by conformal etchingback. The bottom outer spacer 210 can be thicker than the dielectricinner spacer 206 to reduce capacitance. FIG. 12 removing SiO2 207 anddepositing a high-k dielectric layer and metal gate layer 211. FIG. 13illustrates a diagram of etching the high-k dielectric layer and metalgate layer 211 to below the top hard mask 205. FIG. 14 illustrates adiagram of filling with interlayer dielectric (ILD) oxide 212 and thenperforming CMP to the top of hard mask 205.

FIG. 15 illustrates a diagram of etching the hard mask 205 and growing atop source-drain region layer 213 over the first fin to produce thevertical FET. The top source-drain region layer 213 can be a materialsuch as silicon or silicon germanium. The gate contact is located out ofthe paper surface and therefore not shown. A first contact can bedeposited on the top source-drain region layer and a second contact canbe deposited on the bottom source-drain region layer to complete thefinal transistor.

What is claimed is:
 1. A vertical field-effect transistor (FET)structure comprising: a bottom source-drain region disposed on asubstrate of the first type; a recessed first heterostructure layerdisposed on the bottom source-drain region; a first fin disposed on thebottom source-drain region; a first dielectric inner spacer disposed onthe recessed first heterostructure layer; an outer spacer disposed onthe dielectric inner spacer; a high-k and metal gate layer disposed onthe outer spacer, the first dielectric inner spacer, and the channellayer; an interlayer dielectric (ILD) oxide disposed between the firstfin and the outer spacer; a recessed second heterostructure layerdisposed on top of the substrate of the first type and high-k and metalgate layer; a second dielectric inner spacer disposed on the recessedsecond heterostructure layer; and a top source-drain region layerdisposed on the second dielectric inner spacer and recessed secondheterostructure layer resulting in the vertical FET.
 2. The vertical FETof claim 1, wherein the heterostructure layer is silicon germanium. 3.The vertical FET of claim 1, wherein and the channel layer is silicon.4. The vertical FET of claim 1, wherein the first dielectric innerspacer is silicon-boron-carbon-nitride (SiBCN).
 5. The vertical FET ofclaim 1, wherein the first dielectric inner spacer is silicon nitride.6. The vertical FET of claim 1, wherein the bottom outer spacer can bethicker than the dielectric inner spacer to reduce capacitance.
 7. Thevertical FET of claim 1, wherein a first contact is disposed on the topsource-drain region layer.
 8. The vertical FET of claim 1, wherein asecond contact is disposed on the bottom source-drain region layercomplete the final transistor.
 9. The vertical FET of claim 1, whereinthe heterostructure layer has a thickness from about 4 to about 10 nmand ranges there between.
 10. The vertical FET of claim 1, wherein thechannel layer has a thickness from about 10 to about 50 nm and rangesthere between.
 11. The vertical FET of claim 1, wherein a hard maskliner is disposed on the sides of the dielectric inner spacer.
 12. Thevertical FET of claim 11, wherein the hard mask liner is siliconnitride.
 13. The vertical FET of claim 1, wherein the bottomsource-drain region layer is silicon.
 14. The vertical FET of claim 1,wherein the bottom source-drain region layer is silicon-germanium. 15.The vertical FET of claim 1, wherein the first fin is formed by using areactive ion etching (RIE) process.
 16. The vertical FET of claim 1,wherein the dielectric inner spacer is formed by conformal depositionand then conformal etch-back.
 17. The vertical FET of claim 1, furthercomprising an additional bottom source-drain region layer that isepitaxially grown prior to depositing the outer spacer on top of thebottom source-drain region layer.
 18. The vertical FET of claim 1,wherein an interface between the dielectric inner spacer and therecessed second heterostructure layer has a convex shape.
 19. Thevertical FET of claim 1, wherein the second dielectric inner spacer issilicon-boron-carbon-nitride (SiBCN).
 20. The vertical FET of claim 1,wherein the second dielectric inner spacer is silicon nitride.